Medical
Life Sciences
Information Communication
Environment
Energy
Manufacturing Technology
Social Infrastructure
Frontier
Human and social sciences
Creating three-dimensional heterogeneous integration technology (chiplet integration technology) and bio-adaptive flexible hybrid electronics (FHE) to support next-generation AI and edge computing infrastructure.
- Overview of Technology
As a global leader in three-dimensional stacking (3D-IC) and chiplet integration technologies, which are driving performance improvements in next-generation semiconductors, our laboratory has spearheaded research in chip-to-wafer type three-dimensional integration for over 20 years. Utilizing unique technologies, including "self-alignment packaging" that leverages the surface tension of droplets, we have tackled the challenging trade-off between positional accuracy and throughput, contributing to the realization of ultra-high-speed, low-power AI chip systems.
Furthermore, we have developed "dilet" technology, which miniaturizes silicon chips and embeds them in flexible substrates, establishing a platform that enables high-performance device mounting on curved surfaces. This has made significant contributions to the integration and applied research of flexible devices, such as wearable systems that naturally fit the arm, blood vessel visualization sheets, and low-power phototherapy devices that integrate chips and fine wiring into hydrogels primarily composed of water.
From basic research to social implementation utilizing GINTI, we are promoting consistent technological development and opening up new possibilities in semiconductor integration technology.- Comparison with Conventional Technology
Compared to conventional planar mounting, vertical stacking of chips (3D-IC) shortens wiring length and dramatically improves signal transmission capability and energy efficiency. Furthermore, self-alignment enables the simultaneous placement of tens of thousands of tiny chips at ultra-high speed and precision
- Features and Uniqueness
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At IEDM2005, we demonstrated the world's first chip-to-wafer 3D stacking, and since then, we have continued to showcase our achievements at IEDM, leading the way in industrial applications. By using the surface tension of droplets for self-alignment, we have achieved both nano-precision and high throughput, and have established dielet technology that conforms to flexible substrates, as well as die-level 3D-ICs utilizing existing ICs. Furthermore, through collaboration with GINTI and venture companies, we are promoting high-speed prototyping and social implementation.
- Practical Application
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Applications are envisioned in areas such as HPC, edge AI, and medical devices. We anticipate collaboration with materials and equipment manufacturers to co-create new materials and processes, as well as design and fabless companies exploring innovative structures.
- Keywords
Researchers
Graduate School of Biomedical Engineering
Takafumi Fukushima, Professor
In addition to being the world's first to demonstrate "Chip-to-Wafer" stacking technology for 3D-ICs, our laboratory's major strengths lie in its advanced process integration capabilities, utilizing GINTI, a prototyping center for 300 mm wafers. Based on micro- and nano-fabrication and semiconductor packaging engineering, we are promoting the systematization of "holistic integration engineering," which goes beyond individual component technologies and integrates multiple fields such as design, materials, processing, measurement, and heat dissipation to achieve high performance and multi-functionality in semiconductor systems. This comprehensive research approach has led to a wide range of collaborative research with material, equipment, and device manufacturers both in Japan and overseas, and we continue to contribute to the development of advanced back-end processing technologies through industry-academia collaboration.
