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High-speed and low-power asynchronous Network-on-Chip system based multiple-valued current-mode logic

update：2020-06-16
 
 
 
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Global intra-chip interconnection complexity not only limits the clock frequency, but causes clock-skew problems in synchronous system. Asynchronous control-based circuit design, where timing is managed locally, is one of the possible approaches to solve the above serious interconnection problem because the asynchronous design has many features which are low power dissipation, high speed and robustness. However, communication-steps overhead caused by handshaking much would generally affect the cycle time.
In our approach, a high-speed asynchronous data-transfer scheme is proposed based on multiple-valued encoding and current-mode circuits. The multiple-valued encoding enables to improve communication protocol essentially. Moreover, the current-mode circuits which has high-driving capability makes it possible to perform high-speed intra- and inter-chip network. By using this method, we expect that we can conduct effective collaborative research in high-speed and low-power communication LSIs such as a many-core LSI and a multi-module NoC.

Researchers

Research Institute of Electrical Communication

HANYU Takahiro , Professor
PhD of Engineering

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Publications
Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, and Takahiro Hanyu, "High-Throughput Low-EnergyContent-Addressable Memory Based on Self-Timed Overlapped Search Mechanism," Proc. International Symposium on Asynchronous Circuits and Systems (ASYNC), pp.41-48, May 2012.

Naoya Onizawa, Atsushi Matsumoto, and Takahiro Hanyu, "Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling," IEICE Transactions on Fundamentals, vol. E95-A, no. 6, pp.1018-1029, June 2012.
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